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ADVANCE INFORMATION
DS3003 - 3.0
VP1058
8-BIT, 25MHz, VIDEO FLASH ADC (SINGLE + 5V SUPPLY)
The VP1058 is a low power analog-to-digital flash converter which requires no preceding sample and hold stage. Operating from a single +5V supply, it is capable of digitising analog signals with frequencies up to the Nyquist limit. Output data is available in four possible 8-bit formats, selectable via two digital control inputs, giving either true or inverted code in binary or offset twos' complement.
D7 MSB D6 D5 D4 DGND DVCC AGND AGND AGND DVCC DGND NLINV D3 D2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
NMINV VRM VRB AVCC NC AIN NC AIN NC AVCC VRT CONV D0 LSB D1
FEATURES
s s s s s s s s s s s 8-Bit Resolution 25MHz Conversion Rate 60MHz 3dB Analog Input Bandwidth Single +5V Supply Operation Low Power Consumption (Typically 670mW) +3V to +5V Analog Input Range Selectable Data Format TTL Compatible Direct Replacement for TDC 1058 or CXA 1096P Low Cost No Missing Codes - Guaranteed
DP28 DG28
APPLICATIONS
s s s s s s Digital Television Computing Radar Medical Imaging Nucleonics Low-Cost, High-Speed Data Conversion
1 28
VP1058
OPERATING TEMPERATURE RANGE
Commercial 0C to 70C (Still - Air ambient)
ORDERING INFORMATION
VP1058 F CG DPAS (Commercial - Plastic DIL Package, DP28) VP1058 F CG HPAS (Commercial - Quad Plastic J Lead Package, HP28) VP1058 F CG DGAS (Commercial - Ceramic DIL Package, DG28)
HP28
Pin Function Pin Function Pin Function Pin Function
ABSOLUTE MAXIMUM RATINGS
Supply voltage Analog input, AIN Reference voltage VRT, VRB Reference voltage VRT, VRB Digital inputs Mid-ref input current Digital output current Voltage between AGND and DGND Voltage between AVCC and DVCC +7V VCC +0.5 VCC +0.5 2.5V VCC -50mA to +50mA -20mA to +20mA -0.5V to +0.5V -0.5V to +0.5V
1 2 3 4 5 6 7
D7 MSB D6 D5 D4 DGND DVCC AGND
8 9 10 11 12 13 14
AGND AGND DVCC DGND NLINV D3 D2
15 16 17 18 19 20 21
D1 D0 LSB CONV VRT AVCC NC AIN
22 23 24 25 26 27 28
NC AIN NC AVCC VRB VRM NMINV
Fig.1 Pin Connections (Top View)
VP1058
NMINV NLINV CONV
28 12 17 6, 10 19.25 AVCC DVCC
VRT
18 R 16 15 R 14 D0
ENCODER
VRM AIN 27 21, 23 R
8
D LATCH
13 4 3 2 MSB
TTL/CMOS OUTPUTS
AGND 7, 8, 9 VRB R
R x 256
1 5, 11
D7 DGND
26
Fig.2 Internal block diagram
PIN DESCRIPTIONS
Pin No. 1 2-4 5, 11 6, 10 7-9 12 13 - 15 16 17 18 19, 25 20, 22, 24 21, 23 26 27 28 Function D7 D6 - D4 DGND DVCC AGND NLINV D3 - D1 D0 CONV VRT AVCC NC AIN VRB VRM NMINV Most significant bit (output data bit 7) Output data bits 6 to 4 Digital ground Digital supply pin (+5V) Analog ground Not Least significant bits INvert - inverts data D0 to D6 when taken low Output data bits 3 to 1 Least significant bit (output data bit 0) Clock input - the rate of input (CONVert) clock signal determines the ADC sampling rate Top of reference resistor chain Analog supply pin Not connected Analog input pin Bottom of reference resistor chain Midpoint of reference resistor - can be used for linearity adjustment Not Most significant bit INvert - inverts data bit D7 when taken low Description
THERMAL CHARACTERISTICS Storage Temperature Range -65C to +150C Maximum Junction Operating Temperature +175C Lead Temperature (soldering 60 seconds) 300C DP HP DG Junction to Ambient jA 55 57 44 C/W Junction to Case jc 14 15 9 C/W
RECOMMENDED OPERATING CONDITIONS Supply Voltage 5V 0.25V Reference VRT 5V 0.1V Reference VRB 3V 0.1V AVCC to DVCC 0V 50mV Analog Input 4V 1V
VP1058
ELECTRICAL CHARACTERISTICS
These characteristics are guaranteed over the following conditions conditions (unless otherwise stated): VCC = +5V 0.25V, Tamb = 25C DC CHARACTERISTICS Value. Characteristic Conditions Symbol Temp Test level Units Min. Typ. Max. Power Supply Supply voltage Supply current Power dissipation Analog Input Input range Input bias current 3dB bandwidth Input capacitance Reference Ladder Ladder resistance Ladder voltage (top) Ladder voltage (bottom) Ladder offset (top) Ladder offset (bottom) Ladder temp. coeff. Digital Inputs Logic '1' voltage Logic '0' voltage Logic '1' current Logic '1' current Logic '0' current Digital Outputs Logic '1' voltage Logic '0' voltage Static performance Differential non-linearity Integral non-linearity
AVCC/DVCC ICC P AIN IIN f3dB CIN RD VRT VRB VRTO VRBO RTC VIH VIL IIH IIH IIL VOH VOL DNL INL
Full Full 25 Full 25 Full Full 25 25 Full 25 Full Full 25 25 Full Full Full Full Full Full Full 25 Full 25 Full 25 Full 25
4 4 1 4 1 4 4 4 4 4 1 4 4 5 5 5 4 4 4 4 4 4 1 4 1 4 4 4 4
4.75 95 105 500 540 VRB 60 125 125 670 670 150 60 30
5.25 165 150 900 830 VRT 500
V mA mA mW mW V A MHz pF
AGND/DGND = 0V
50 75 2.5
90 145 100 125 V 5.0 AVCC + 0.1 V 3.0 mV 15 mV 5 /C 0.33 0.8 350 75 -150 V V A A A V V V V LSB LSB LSB LSB
VRT > VRB
2.0
VI = VCC = MAX VI = 2.4V, VCC = MAX VI = 0.4V, VCC = MAX Into a standard LSTTL load
2.4 2.4 0.4 0.4 0.5 0.5 0.5 0.5
AC CHARACTERISTICS Characteristic Clock min.high Clock min.low Max. conversion rate Aperture delay Output data delay Output hold time Aperture Jitter Dynamic Performance Differential non-linearity Integral non-linearity S/N ratio Symbol tPW1 tPW0 fMAX tAD tD tHO Temp Test level Full Full Full 25 25 Full 25 Full 25 25 25 25 Full 25 Full 25 Full 25 4 4 4 5 4 4 4 4 5 1 1 1 4 4 4 4 4 1 4 4 Value. Min. 15 15 25 3 25 30 5 5 50 -0.85 0.5 1 45 44.5 44.0 43.5 43.5 43.0 7.2 7.1 7.0 +1 2 Typ. Max. ns ns MHz ns ns ns ns ns ps LSB LSB dB dB dB dB dB dB bits bits bits Units Conditions
AIN at FS & 12.5MHz With standard LSTLL load fCLK = 25MHz AIN at FS & 1.019MHz AIN = 1.019MHz AIN = 1.019MHz AIN = 2.438MHz AIN = 2.438MHz AIN = 4.388MHz AIN = 4.388MHz AIN = 1.019MHz AIN = 2.438MHz AIN = 4.388MHz
DNL INL SNR
Effective No. of bits
ENOB
VP1058
ELECTRICAL CHARACTERISTICS DEFINITIONS
Analog Bandwidth The analog input frequency, at which the spectral power of the fundamental frequency as determined by Fast Fourier Transform analysis, is 3dB down on the DC level. Aperture Delay The delay between the falling edge of the CONV signal and the instant at which the analog input is sampled. Aperture Jitter The variation between successive samples of the aperture delay. Conversion Rate The maximum rate at which the converter will run. Differential Non-Linearity (DNL) The deviation of any code width from an ideal LSB step. Effective Number of Bits (ENOB) This is a measure of the dynamic performance which is calculated from the following expression.: ENOB = SNR-1.76 6.02 SNR is the signal-to-noise ratio, in decibels, at the test frequency. Integral Non-Linearity (INL) The deviation of the centre of each code from a reference line which has been determined by a least squares curve fit. Output Data Delay The delay between the 50% point of the rising edge of the CONV signal and the 50% point of any data output change. Reference Ladder Offset The voltage error at the ends of the resistor chain caused by the lead frame and bond wire. Signal-to-Noise Ratio (SNR) The ratio of the RMS signal amplitude to the RMS value of 'noise' which is defined as the sum of all other spectral components including harmonics but excluding DC with a full scale analog input signal. Test Levels Level 1 - 100% production tested Level 2 - 100% production tested at 25C and sample tested at specified temperatures Level 3 - Sample tested only Level 4 - Parameter is guaranteed by design and characteristics testing Level 5 - Parameter is a typical value only
CONVERSION TIMING
Operation of the VP1058 requires that an external clock be applied to the CONV (convert) pin. This CONV signal synchronises the sampling, conversion, and output stages of the devices as shown in the timing diagram (Fig.3). The analog input is sampled when the comparator array is latched after a rising edge on the CONV pin. This rising edge also causes the result of the previous sample to be transferred to the outputs. Data at the outputs is latched at the same time as the 255 to 8 encoding of the current sample. Both these operations are performed on the falling edge of the CONV signal. This results in a 'pipeline' delay which means that the
SAMPLE N SAMPLE N+1
digital result of sample 'N' is available for acquisition by external circuitry whilst sample 'N+2' is being taken. The time interval between a rising edge on the CONV pin and the comparators latching is the aperture delay time (tAD). This time may be subject to small variations mainly due to temperature and component matching. The short term uncertainty in the aperture delay time is specified by the aperture jitter (or aperture error). Output data becomes valid after tD (output data delay). Data remains valid for at least tHO (output hold time) after the rising edge of the CONV pin.
SAMPLE N+2
SAMPLE N+3
VIN tAD tCYC CONV tD DATA OUTPUT 4V DATA VALID N-2 0V PIPELINE DELAY DATA VALID N-1 tpw1 tpw0 DATA VALID N tHO DATA VALID N+1
Fig.3 Timing diagram
VP1058
GENERAL CIRCUIT DESCRIPTION
The VP1058 employs a 'flash' architecture consisting of a reference resistor chain, an array of 256 comparators, encoding logic, and a full 8-bit D-type output latch. The 255 reference levels generated by the resistor chain are compared with the analog input signal by the comparator array. This produces a thermometer code which the encoding logic coverts into an 8-bit word. The D-type latch accepts this data and holds the outputs until the next conversion. The format of the output data is determined by the NLINV and NMINV control lines. Analog Input The maximum amplitude and offset of the input is defined by the setting of the two reference voltages VRB and VRT. A signal outside this range will cause the output to be either fullscale positive or full-scale negative, depending on whether the signal is off scale in the positive or negative direction. For optimum performance, the input signal should be biased at +4.0V with a 2V peak-to-peak amplitude. The necessary gain, offset and low impedance drive required for the input signal can be provided by use of a high slew rate ADC driver. Reference Voltage The reference chain between pins VRB and VRT is formed of 256 series resistors and has a total resistance of approximately 90. A mid-reference pin, VRM, is provided for precise setting of the integral linearity, although adjustment is not necessary to meet the data sheet specification. The VP1058 will convert analog signals in the range VRB < AIN < VRT, where VRB and VRT are in the range +3V to +5V. (The design of the VP1058 has been optimised for VRB = 3V and VRT = 5V). All reference pins should be adequately decoupled close to the device. Output Format The output data format is controlled by the logic levels at the NLINV and NMINV pins as shown on the output coding table. These inputs are active low and may be tied to DVCC for logic '1' or DGND for logic '0'. Both inputs are considered DC controls and as such should only be altered while the converter is in the steady state.
VRT
AVCC
AIN
40A AGND
40A
VRB
Fig.4 Analog input
DVCC
OUTPUT
DGND
Fig.5 TTL output stage
Input voltage Code 20.V Full Scale 2.048V Full Scale 8.0mV Step 7.8431mV Step 5.0V 5.0V 4.9922V 4.9922V
q q
Binary True NMINV = 1 NLINV = 1 0000 0000 0000 0001
q
Offset 2s' complement Inverted 0 0 1111 1111 1111 1110
q
000 001
q
True 0 1 1000 0000 1000 0001
q
Inverted 1 0 0111 1111 0111 1110
q
127 128 129
q
4.0039V 3.9961V 3.9882V
q
3.9840V 3.9760V 3.9680V
q
0111 1111 1000 0000 1000 0001
q
1000 0000 0111 1111 0111 1110
q
1111 1111 0000 0000 0000 0001
q
0000 0000 1111 1111 1111 1110
q
254 255
3.0079V 3.0V
2.9680V 2.960V
1111 1110 1111 1111
Table 1 Output coding
0000 0001 0000 0000
0111 1110 0111 1111
1000 0001 1000 0000
VP1058
APPLICATION NOTES
As with all high speed analog-to-digital converters, careful consideration must be given to circuit layout. The best performance from the VP1058 can be achieved by use of separate analog and digital ground planes. Ideally these should be connected at a point close to the device. This will reduce the amount of digital switching noise fed back into the analog section of the converter, so aiding device performance. Supply line decoupling is important when dealing with mixed analog and digital signals, as they can provide a feedback path from the digital output currents. Therefore, the VP1058 should be decoupled close to the device supply pins with good quality high frequency, low inductance capacitors. Due to the high clock rates, long clock lines to the device should be avoided to reduce noise pick up. A typical applications circuit is shown below. The analog input amplifier should be a wideband, high slew rate op-amp used to drive the input directly. A stable reference is needed for both input offset and gain control (e.g. REF12Z micropower voltage reference as shown in Fig.6). Both analog input pins should be connected close to the device with the input amplifiers feedback loop closed at the point. The reference inputs should be adequately decoupled to ground so as to limit the effects of system noise on conversion accuracy. A capacitor at the mid-reference point (as shown) may be useful in correcting any inherent reference ladder skew. The circuit will accept a 1V p-p video signal and level shift and multiply it to provide the recommended 2V p-p signal to drive the VP1058.
+12V 3.3k 1k + 0.1 6K2 2K TAB1043
+12V 390 2N2222
+5V AVCC
+5V DVCC 0.1 6, 10 DVCC
+5V AVCC 0.1 19, 25 AVCC
1N4148 DB7 DB6 18 VRT DB5 DB4 1 2 3 4 13 14 15 16
0.1
VP1058
2.9k 0.1 + 3k REFGAIN AD842 OR SIMILAR + VOUT 21 23 17 REF12Z (1.22V REFERENCE) TAB1043 2N2907 +5V 27 0.1 26 VRB
DB3 DB2 DB1
VRM
DB0
NMINV LNINV
28 12
1k VREF
AIN AIN CONV DGND 5, 11 AGND 7, 8, 9
2k
1.3k
ANALOG INPUT (VANIN) 50
1k 1k 1k VO
0.1
2k OFFSET 0.1 CLOCK
Fig.6 Typical applications circuit
VP1058
VP1058
HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576
CUSTOMER SERVICE CENTRES * FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax : (1) 64 46 06 07 * GERMANY Munich Tel: (089) 3609 06-0 Fax : (089) 3609 06-55 * ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 * JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510 * NORTH AMERICA Scotts Valley, USA Tel (408) 438 2900 Fax: (408) 438 7023. * SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872 * SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 * TAIWAN, ROC Taipei Tel: 886 2 5461260. Fax: 886 2 7190260 * UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (0793) 518510 Fax : (0793) 518582 These are supported by Agents and Distributors in major countries world-wide. (c) GEC Plessey Semiconductors 1994 Publication No. DS3003 Issue No. 3.0 June 1994 TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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TECHNICAL DOCUMENTATION - NOT FOR RESALE

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